Tag: RISC-V

RISC-V SBCs

I’ve got some RISC-V SBCs, an AWOL Nezha board, and a Mango Pi MQ Pro. Both are based on the AllWinner D1 SoC. As recently I came across an SD card image builder that generates an Arch Linux image for these type of boards. https://github.com/sehraf/riscv-arch-image-builder This script combines OpenSBI (first stage bootloader), u-boot (second stage…


RISC-V ‘clones’ of the STM32F103 (part 2)

This is part 2 of the look at the GD32VF103 and the CH32V103. Microcontrollers with a RISC-V RV32IMAC core and STM32F103 compatible peripherals. As stated in the pervious article, their main difference is how the interrupts are handled. Of course, both can do interrupts as per RISC-V standard, the main issue is the fact the…


Some notes about RISC-V compilers

As I’ve written in my previous post, I’ve been playing around with RISC-V recently. As part of building for RISC-V a compiler is required. As I am an ArchLinux user, I query pacman for the compiler. In the community repository I’ve found riscv64-elf-gcc. Additionaly, I need a C library, which is in the riscv32-elf-newlib package….


RISC-V ‘clones’ of the STM32F103 (part 1)

RISC-V is the new hot thing. And so, there are some Chinese MCU manufacturers making RISC-V versions of their 32F103 clones. GigaDevice has their GD32VF103 around since 2019, and WinChipHead introduced their CH32V103 last year. Now, let’s have a look at these chips. These chips are basically, a RISC-V core attached to the 32F103 peripherals….